`timescale 1ns/1ns
module tx_test;
  reg clk,rst,Tx_en,bps_clk;
  reg[7:0] tx_data;
  wire Tx_pin_out;
  tx u2(clk,rst,Tx_en,tx_data,bps_clk,Tx_pin_out);
  initial
  begin
    clk=1;rst=0;Tx_en=0;bps_clk=0;tx_data=0;
    #10 rst=1;
    #10 Tx_en=1; bps_clk=1;
    #10 tx_data[7:0]=1001101;
    #100 $stop;
  end
  always #5 clk=~clk;
  initial $monitor($time, , ,"clk=%b rst=%b Tx_en=%b tx_data=%b bps_clk=%b Tx_pin_out=%b",clk,rst,Tx_en,tx_data,bps_clk,Tx_pin_out);
endmodule
  
  
    

  
